Core_EDA

# Dynamic IR analysis

## Road map (From Megy Wang):

470 

## Correlation plan

### We need a VCD generator (toggle comb. cells at given times, disable VCD propagation in RK)

  a. what if no toggle at all?

  b. what if only inverter toggles?

  c. what if several inverter toggle?

  d. what if FF toggle? (with/without Q toggle?)

### We need to verify Resistance (enhance analyze_pg_resistance, report_pg_resistance. similar results from RK)

  a. min-path compare

  b. min-path length compare

  c. effective path compare

  d. resistance compare with pad (case006)

  e. resistance compare with psw (case002)

  f. resistance correlation with long via (case00l, 005)

  g. resistance check BFFORF IR ANA;rYSIS

### We need to correlate current, which means:

  a. rise/fall charge

  b. rise/fall width

  c. rise/fall peak

  d. FF cells with above

  e. rise/fall slope 

  f. detailed shape polynomial

### We need to verify capacitance (need investigation) 

### Flow level verify (combined PG algorithm)

  a. SPICF level verify

  b. node reduction impact

  c. by-pass impact

### VCD correlation method (From Daisy Li)

DVP binary folder□面叩这叩目叩D etc/sh/grep_vcd.sh

用田D 

grep_vcd.sh $vcd_file $nets_file Nets file formatD

instA/instB/instC/pinA instA/instB/instD/netl

### Cap check

Intrinsic cap can be annotate by below methodology:

set—emir—model [get—cells -hierar -filter "is—memory==true"] -intrinsic—cap l20

analy江e—power—network -dynamic -vector—file xxx.vcd -start—time xx -end—time xx report—inst—dynamic—irdrop—info > cap—anno.log

show—emir—correlation—result \

	-test—file cap—anno.log \

	-test—index—name inst—name \

	-test—value—name max—ir—drop—among—cycles 

	-ref—file non—anno.log \

	-ref—index—name inst—name \

	-ref—value—name  max—ir—drop—among—cycles

髻 plot procedure is painful, skip for now

Example max_ir_drop_among_cycles with/without intrinsic cap annotation 

Left: ir distribution between annotated IR and un-annotated IR

Right: y axis is annotated IR, x axis is un-annotated IR

### Current check

In vector based IR analysis, and ref-tool dynamic IR analysis, switching current is generated according toD

switching window (from twf) 

load cap  (from spef) 

clock period (from twf) 

slew (from twf)

With above information, tool can generate switching current. 

An example for dynamic current replay:

270 

## Speed up Dynamic IR Analysis: (From Bob, PiJun, YingShi discussion)

1.Solver level by-pass (RHS norm check, e.g.)

2.Step I, V by-pass (Realized by Dr. PiJun Liu, DanPing, 4X speed up)

```

髻 dyn-curr by-pass threshold, default 0.0l mA 

set—app—var ir dynamic—sim—abstol 0.0l

髻 dyn-volt by-pass threshold, default 0.000l V (0.l mV) 

set—app—var ir dynamic—sim—vnstol 0.000l

```

# The optimal combination of abstol and vnstol (for DTH case)

case003 0-95.45n abstol=1e-4 &vnstol=4e-5 (min_pg_simDmin_pg_tw) results as below: 

VP bypassD叩果叩证DDOD度叩叩D且叩影叩DtargetDcorrelation

![](clipboard-202503292143-aumw7.png)

DDDVP bypassD叩能叩D叩升叩DDDDD相叩caseD叩步叩次叩真DtFEDD化叩DDbypass 组叩包叩1e-4/1e-5 D 1-4/4e-5;SC_＊＊ 标叩D叩应DSlove Counts□

![](clipboard-202503292143-9crbc.png)

3. By-area adjust tolerance

4. relative and absolute tolerance

5. Linear fitting between actual solving and by-pass