Core_EDA

# EDA Traveller

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50[[2023 session advanced group]] (solver 新叩D)

## Achieves before 2023

* Step n: Incremental VLSI Training QA (from web youtube, etc..)

* Step n+1: Incremental VLSI Training QA from DTH

* Step n+2: Giga Expert Training DDDDDDDD 

* Step n+n: EDA news and market link

##EDA traveller 2024

### Group 1 computer architecture D Group winner group 1 O叩D SiQi (1500 OOD ZhiHao D 1400 O叩D 

LinJun and ZhengYu D 13000 

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|TR_1|attachment:"Processing_near_Memory_jiamin.pptx"|JiaMin|TBA|DanPing|

|TR_3|attachment:"memory_controller_sqchen.pptx"|SiQi|attachment:"Prefetching_jiamin.pptx"|JiaMin|

|TR_4|attachment:"Prefetching_II_wyxiong.pptx"|WangYang|attachment:"Flash_Memory_and_Solid_State_Drivers_zhihao.pptx"|ZhiHao|

|TR_5|attachment:"Flash_Memory_and_Solid_State_Drives_II_heng.pptx"|Heng|attachment:"Parallelism_and_Heterogeneity_wangyang.pptx"|WangYang|

|TR_6|attachment:"Multiprocessor_linjun.ppt"|LinJun|attachment:"cache_coherence_chunyan.pptx"|ChunYan|

|TR_7|attachment:"simd_and_gpu_architectures_bowen.pptx"|Bowen|attachment:"gpu_programming_keliang.pptx"|KeLiang|

|TR_8|attachment:"virtual_memory_release_zhengyu.pptx"|ZhengYu|attachment:"Cache_Design_and_Management_heng.pptx"|Heng|

### Group 2: Heterogeneous computing (GPU/TPU) (Group winner group 2 O叩DDD Dr. Zhuang and LePing (1400 OOD DD D 1300 O叩D Dr. Zhuang (10 00 )

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|TR_1|attachment:"Parallel_Patterns_Prefix_Sum_leping.pptx"|LePing|attachment:"Parallel_Patterns_Sparse_Matrices_xyshi.pptx"|Dr. Shi XueYang|

|TR_3|attachment:"Parallel_Patterns_graph_serach_xijing.pptx"|XiJing|attachment:"Parallel_Patterns_Programming_Heterogeneous_Computing_Systems_with_GPU_and_other_Accelerators_weike.pptx"|WeiKe|

|TR_4|attachment:"Parallel_Patterns_simd_and_dynamic_parallism_hongguang.pptx"|HongGuang|attachment:"Parallel_Patterns_simd_and_dynamic_parallism_hongguang.pptx"|HongGuang|

|TR_5|attachment:"GPU_software_hierarchy_qingyu.pptx"|QingYu|attachment:"GPU_Memory_Hierarchy_dr_zhuang.pptx"|Dr. Zhuang ShiHao|

|TR_6|attachment:"GPU_Performance_Consideration_dr_zhuang.pptx"|Dr. Zhuang ShiHao|attachment:"GPU_matrix_transpose_reduction_shaobo.pptx"|ShaoBo|

|TR_7|attachment:"Parallel_Patterns_convolution_siyan.pptx"|SiYan|attachment:"Parallel_Patterns_Histogram_Computation_yingjie.pptx"|YingJie|

|TR_8|attachment:"Advanced_Tiling_For_Matix_Multiplication_qiongzhang.pptx"|Qiong|attachment:"Hadoop_Architecture_and_HDFS_architecture.pptx" <u>and</u> attachment:"Hadoop_Architecture_and_HDFS_architecture_chunyan.pptx"|ChunYan|

### Group 3: Chip design and EDA flow (Group winner group 3 O叩D DD (1500 OOD oo D 1400 O叩D DD (11

00 )

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|TR_1|attachment:"Traveller_PR_flow_v1.0_zhenming.pdf"|ZhenMing|attachment:"RTL_Synthesis_intro_daisy.pptx"|Daisy|

|TR_2|synthesis toolDDD步叩DOD (invited sharing)|ZeBang|attachment:"digital_backend_physical_design_implementation_icc_huiniupptx.pptx"|HuiNiu|

|TR_3|attachment:"A_quick_look_at_DFT_daisy.pptx"|Daisy|DFT flow (invited sharing)|XinWang|

|TR_4|attachment:"Calibre_huiniu.pptx" <u>and</u>  attachment:"physical_verification1_huiniu.pptx"|HuiNiu|attachment:"STARRC_upload_JingLin.pptx"|Jane|

|TR_5|attachment:"Traveller_PT_ZhenMing.pptx"|ZhenMing|attachment:"totem_v1.2_jiaxiao.pptx"|JiaXiao|

|TR_6|attachment:"redhawk_JingLin.pptx"|Jane|attachment:"seahawk_v1.2_jiaxiao.pptx"|JiaXiao|

|TR_7|attachment:"K-lib_introduction_HaiAn.pptx"|HaiAn|attachment:"VCS_intro_Siqi_Chen.pptx"|SiQi|

### Group 4: Parallel computing application (Group winner group 4 O叩D DD (1100 OOD DD D 1000 O叩D 喜叩 and D0 (9 00 )

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|TR_1|-|-|attachment:"communication_optimal_matrix_mul_xijing.pptx"|Xijing|

|TR_2|attachment:"Sources_of_Parallelism_and_Locality_in_Simulation_yingjie.pptx"|Yingjie|attachment:"An_introduction_of_Cuda_and_GPUs_shumiao.pptx"|Shumiao|

|TR_3|attachment:"lecture08_data_parallel_algorithm_demmel22_lpwang.pptx|lePing|attachment:"graph_partition_shaobo.pptx|Shaobo|

|TR_4|attachment:"distributed_memory_machine_and_program_qiong.pptx"|Qiong|attachment:"Advanced_MPI_and_Collective_Communication_Algorithm_shumiao.pptx"|Shumiao|

|TR_5|attachment:"densela_1_parallel_matxi_multiplication_xyshi.pptx"|Dr. Shi|-|-|

|TR_6|attachment:"Ray_A_universal_framework_for_distributed_computing_stoica22_qingyu.pptx"|QingYu|attachment:"Sparse_Matrix_Vector_Multiply_SpMV_and_Iterative_Solvers_bowen.pptx"|Bowen|

|TR_7|attachment:"Dynamic_Load_Balancing_demmel22_siyan.pptx"|SiYan|attachment:"parallel_graph_algorithm_Siqi_Chen.pptx"|SiQi|

## EDA traveller 2023

{{thumbnail(eda_traveller.jpg, size=555)}}

### 2023 EDA Traveller Mar to May sessions

TBA

### Group 1 VLSI and EDA flow: D Group winner top three: HaiAn(16), ZhengYu(12), Daisy(9)0

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|TR_01|TR_2023_01_CMOS_Logic.pptx|Qiong 2023/03/20|

|TR_02|TR_2023_02_chip_fabrication.pptx|Daisy 2023/03/20|

|TR_03|TR_2023_03floorplan_placement_Routing.pptx|JiaXiao, XiaoHu, SiYan 2023/03/21|

|TR_04|TR_2023_04_Static_timing_analysis.pptx|ZhiHao, ZhenMing 2023/03/23|

|TR_05|TR_2023_05_Chip_Finishing_Sign_Off.pptx|YingJie Tang, Sheng Huang 2023/03/27|

|TR_06|TR_2023_06_sdp_Power_Analysis.pptx|ZhengYu Wang 2023/03/28|

|TR_07|TR_2023_07_power_calculation_flow.pptx|LangYun Zeng 2023/03/28|

|TR_08|TR_2023_08_IR_drop.pptx|ShuMiao Li 2023/04/10|

|TR_09|TR_2023_09_low_power_UPF.pptx|XiJing Yao 2023/04/10|

|TR_10|TR_2023_10_Free45nm_PDK_design.pptx|HaiAn 2023/04/11|

**Note:** OCL PDK flow in: Verilog_to_manufacture_lecture , ZhenMing will follow up to setup HVP tutorial demo in cutbuild.

### Group 2 spice and liberty characterization D Group winner top three: LePing(15), LinJun(12),

HaiAn(11)0

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|--|--|--|

|TR_11|TR_2023_11_spice_introduce_usage.pptx|JiaXiao 2023/04/13|

|TR_12|TR_2023_12_SPICE_SIMULATION.pptx spice_simulation_case.zip|LePing2023/04/17|

|TR_13|TR_2023_13_SPICE_NUMERIC_METHOD.pptx|JiaMin, Qiong 2023/04/18|

|TR_14|TR_2023_14_klib_basic_knowledge.pptx|Danping 2023/04/20|

|TR_15|TR_2023_15_intro_liberity.pptx TR_2023_15_k_lib_timing.pptx|LinJun 2023/04/24 and Hui 2023/04/24|

|TR_16|TR_2023_16_Low_Power_Cell.pptx|ZhenMing 2023/04/25|

|TR_17|TR_2023_17_Memory_IP_Macro.pptx|LangYun 2023/04/27|

|TR_18|TR_2023_18_Free45nm_kl_ccsp.pptx|HaiAn 2023/04/27|

(Homework: Why switching power is 0.5CVV?) why_sw_pow_is_0d5cvv.pptx

TODO Ask SiQi to import demo k-lib flow into emir reg db and wiki #19681

### Group 3 interconnection and signal integrity D Group winner top three: LePing(17), JiaMin(13), JingLin(12)0

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|TR_19|TR_2023_19_cmp_resistance_extract_flow.pptx|Jing Lin 2023/05/08|

|TR_20|TR_2023_20_PG_wire_parasitic_and_extraction.pptx|ChunYan 2023/05/08|

|TR_21|TR_2023_21_parasitic_and_spef.pptx.pptx|HaiAn 2023/05/29|

|TR_22|TR_2023_22_signal_wire_delay_pi_rom.pptx|LePing 2023/05/30|

|TR_23_a|TR_2023_23_CPM_introduction.pptx|WangYang Xiong 2023/06/01|

|TR_23_b|TR_CPM_1_macro_model_based_on_MOR.pptx 00叩叩叩叩DD宏叩叩叩|JiaMin 2023/06/01|

|TR_23_c|TR_CPM_2_MOR_model_order_reduction_20230511.pptx 0叩叩叩D叩|JiaMin 2023/06/01|

|TR_24|TR_2023_24_CSM_introduction_20230605.pptx|WangYang Xiong 2023/06/05|

|TR_25|TR_2023_25_IBIS_Intro.pptx|SiQi Chen 2023/06/08|