EDA Traveller » History » Revision 2
Revision 1 (jun chen, 03/22/2025 12:15 AM) → Revision 2/21 (jun chen, 03/22/2025 12:19 AM)
# EDA Traveller 570 502023 session advanced group (solver 新叩D) ## Achieves before 2023 * Step n: Incremental VLSI Training QA (from web youtube, etc..) * Step n+1: Incremental VLSI Training QA from DTH * Step n+2: Giga Expert Training DDDDDDDD * Step n+n: EDA news and market link ##EDA traveller 2024 ### Group 1 computer architecture D Group winner group 1 O叩D SiQi (1500 OOD ZhiHao D 1400 O叩D LinJun and ZhengYu D 13000 | | | | | |--|--|--|--| |TR_1|Processing_near_Memory_jiamin.pptx|JiaMin|TBA|DanPing| |TR_3|memory_controller_sqchen.pptx|SiQi|Prefetching_jiamin.pptx|JiaMin| |TR_4|Prefetching_II_wyxiong.pptx|WangYang|Flash_Memory_and_Sol id_State_Drivers_zhihao.pptx|ZhiHao| |TR_5|Flash_Memory_and_Solid_State_Drives_II_heng.pptx|Heng|Parallelism_and_Hetero geneity_wangyang.pptx|WangYang| |TR_6|Multiprocessor_linjun.ppt|LinJun|cache_coherence_chunyan.pptx|ChunYan| |TR_7|simd_and_gpu_architectures_bowen.pptx|Bowen|gpu_programming_keliang.pptx|KeLiang| |TR_8|virtual_memory_release_zhengyu.pptx|ZhengYu|Cache_Design_and_Management_heng.pptx|Heng| ### Group 2: Heterogeneous computing (GPU/TPU) (Group winner group 2 O叩DDD Dr. Zhuang and LePing (1400 OOD DD D 1300 O叩D Dr. Zhuang (10 00 ) ||||| |A |B |C |D | |--|--|--|--| |TR_1|Parallel_Patterns_Prefix_Sum_leping.pptx|LePing|Parallel_Patterns_Sparse_Matrices_xyshi.pptx|Dr. Shi|XueYang| |TR_3|Parallel_Patterns_graph_serach_xijing.pptx|XiJing|Parallel_Patterns_Programming_Heterogeneous_Computing_Systems_with_GPU_and_other_A ccelerators_weike.pptx|WeiKe| |TR_4|Parallel_Patterns_simd_and_dynamic_parallism_hongguang.pptx|HongGuang|Parallel_Patterns_simd_and_dynamic_parallism_hongguang.pptx|HongGuang| |TR_5|GPU_software_hierarchy_qingyu.pptx|QingYu|GPU_Memory_Hierarchy_dr_zhuang.pptx|Dr. Zhuang ShiHao| |TR_6|GPU_Performance_Consideration_dr_zhuang.pptx|Dr. Zhuang ShiHao|GPU_matrix_transpose_reduction_shaobo.pptx|ShaoBo| |TR_7|Parallel_Patterns_convolution_siyan.pptx|SiYan|Parallel_Patterns_Histo gram_Computation_yingjie.pptx|YingJie| |TR_8|Advanced_Tiling_For_Matix_Multiplication_qiongzhang.pptx|Qiong|Hadoop_Architecture_and_HDFS_architecture.pptx|Hadoop_Architecture_and_HDFS_architecture_chunyan.pptx|ChunYan| ### Group 3: Chip design and EDA flow (Group winner group 3 O叩D DD (1500 OOD oo D 1400 O叩D DD (11 00 ) |A |B |C |D |E | |--|--|--|--|--| |TR_1|Traveller_PR_flow_v1.0_zhenming.pdf|ZhenMing|RTL_Synthesis_intro_daisy.pptx|Daisy| |TR_2|synthesis toolDDD步叩DOD (invited sharing)|ZeBang|digital_backend_physical_design_implementation_icc_huiniupptx.pptx|HuiNiu| |TR_3|A_quick_look_at_DFT_daisy.pptx|Daisy|DFT flow (invited sharing)|XinWang| |TR_4|Calibre_huiniu.pptx physical_verification1_huiniu.pptx|HuiNiu|STARRC_upload_JingLin.pptx|Jane| |TR_5|Traveller_PT_ZhenMing.pptx|ZhenMing|totem_v1.2_jiaxiao.pptx|JiaXiao| |TR_6|redhawk_JingLin.pptx|Jane|seahawk_v1.2_jiaxiao.pptx|JiaXiao| |TR_7|K-lib_introduction_HaiAn.pptx|HaiAn|VCS_intro_Siqi_Chen.pptx|SiQi|