EDA Traveller » History » Version 8
jun chen, 03/22/2025 12:51 AM
| 1 | 1 | jun chen | # EDA Traveller |
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| 4 | 570 |
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| 5 | 5 | jun chen | 50[[2023 session advanced group]] (solver 新叩D) |
| 6 | 4 | jun chen | |
| 7 | 1 | jun chen | ## Achieves before 2023 |
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| 9 | * Step n: Incremental VLSI Training QA (from web youtube, etc..) |
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| 10 | * Step n+1: Incremental VLSI Training QA from DTH |
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| 11 | * Step n+2: Giga Expert Training DDDDDDDD |
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| 12 | * Step n+n: EDA news and market link |
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| 13 | |||
| 14 | ##EDA traveller 2024 |
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| 15 | |||
| 16 | ### Group 1 computer architecture D Group winner group 1 O叩D SiQi (1500 OOD ZhiHao D 1400 O叩D |
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| 17 | LinJun and ZhengYu D 13000 |
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| 20 | |--|--|--|--| |
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| 21 | 6 | jun chen | |TR_1|attachment:"Processing_near_Memory_jiamin.pptx"|JiaMin|TBA|DanPing| |
| 22 | |TR_3|attachment:"memory_controller_sqchen.pptx"|SiQi|attachment:"Prefetching_jiamin.pptx"|JiaMin| |
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| 23 | 7 | jun chen | |TR_4|attachment:"Prefetching_II_wyxiong.pptx"|WangYang|attachment:"Flash_Memory_and_Solid_State_Drivers_zhihao.pptx"|ZhiHao| |
| 24 | |TR_5|attachment:"Flash_Memory_and_Solid_State_Drives_II_heng.pptx"|Heng|attachment:"Parallelism_and_Heterogeneity_wangyang.pptx"|WangYang| |
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| 25 | 6 | jun chen | |TR_6|attachment:"Multiprocessor_linjun.ppt"|LinJun|attachment:"cache_coherence_chunyan.pptx"|ChunYan| |
| 26 | |TR_7|attachment:"simd_and_gpu_architectures_bowen.pptx"|Bowen|attachment:"gpu_programming_keliang.pptx"|KeLiang| |
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| 27 | |TR_8|attachment:"virtual_memory_release_zhengyu.pptx"|ZhengYu|attachment:"Cache_Design_and_Management_heng.pptx"|Heng| |
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| 28 | 1 | jun chen | |
| 29 | ### Group 2: Heterogeneous computing (GPU/TPU) (Group winner group 2 O叩DDD Dr. Zhuang and LePing (1400 OOD DD D 1300 O叩D Dr. Zhuang (10 00 ) |
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| 32 | 1 | jun chen | |--|--|--|--| |
| 33 | 8 | jun chen | |TR_1|attachment:"Parallel_Patterns_Prefix_Sum_leping.pptx"|LePing|attachment:"Parallel_Patterns_Sparse_Matrices_xyshi.pptx"|Dr. Shi|XueYang| |
| 34 | |TR_3|attachment:"Parallel_Patterns_graph_serach_xijing.pptx"|XiJing|attachment:"Parallel_Patterns_Programming_Heterogeneous_Computing_Systems_with_GPU_and_other_Accelerators_weike.pptx"|WeiKe| |
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| 35 | |TR_4|attachment:"Parallel_Patterns_simd_and_dynamic_parallism_hongguang.pptx"|HongGuang|attachment:"Parallel_Patterns_simd_and_dynamic_parallism_hongguang.pptx"|HongGuang| |
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| 36 | |TR_5|attachment:"GPU_software_hierarchy_qingyu.pptx"|QingYu|attachment:"GPU_Memory_Hierarchy_dr_zhuang.pptx"|Dr. Zhuang ShiHao| |
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| 37 | |TR_6|attachment:"GPU_Performance_Consideration_dr_zhuang.pptx"|Dr. Zhuang ShiHao|attachment:"GPU_matrix_transpose_reduction_shaobo.pptx"|ShaoBo| |
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| 38 | |TR_7|attachment:"Parallel_Patterns_convolution_siyan.pptx"|SiYan|attachment:"Parallel_Patterns_Histo gram_Computation_yingjie.pptx"|YingJie| |
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| 39 | |TR_8|attachment:"Advanced_Tiling_For_Matix_Multiplication_qiongzhang.pptx"|Qiong|attachment:"Hadoop_Architecture_and_HDFS_architecture.pptx"|attachment:"Hadoop_Architecture_and_HDFS_architecture_chunyan.pptx"|ChunYan| |
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| 40 | 2 | jun chen | |
| 41 | ### Group 3: Chip design and EDA flow (Group winner group 3 O叩D DD (1500 OOD oo D 1400 O叩D DD (11 |
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| 42 | 00 ) |
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| 44 | 3 | jun chen | |||||| |
| 45 | 2 | jun chen | |--|--|--|--|--| |
| 46 | |TR_1|Traveller_PR_flow_v1.0_zhenming.pdf|ZhenMing|RTL_Synthesis_intro_daisy.pptx|Daisy| |
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| 47 | |TR_2|synthesis toolDDD步叩DOD (invited sharing)|ZeBang|digital_backend_physical_design_implementation_icc_huiniupptx.pptx|HuiNiu| |
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| 48 | |TR_3|A_quick_look_at_DFT_daisy.pptx|Daisy|DFT flow (invited sharing)|XinWang| |
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| 49 | |TR_4|Calibre_huiniu.pptx physical_verification1_huiniu.pptx|HuiNiu|STARRC_upload_JingLin.pptx|Jane| |
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| 50 | |TR_5|Traveller_PT_ZhenMing.pptx|ZhenMing|totem_v1.2_jiaxiao.pptx|JiaXiao| |
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| 51 | |TR_6|redhawk_JingLin.pptx|Jane|seahawk_v1.2_jiaxiao.pptx|JiaXiao| |
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| 52 | 1 | jun chen | |TR_7|K-lib_introduction_HaiAn.pptx|HaiAn|VCS_intro_Siqi_Chen.pptx|SiQi| |
| 53 | 3 | jun chen | |
| 54 | ### Group 4: Parallel computing application (Group winner group 4 O叩D DD (1100 OOD DD D 1000 O叩D 喜叩 and D0 (9 00 ) |
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| 57 | |--|--|--|--|--| |
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| 58 | |TR_1|-|-|communication_optimal_matrix_mul_xijing.pptx|Xijing| |
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| 59 | |TR_2|Sources_of_Parallelism_and_Locality_in_Simul ation_yingjie.pptx|Yingjie|An_introduction_of_Cuda_and_GPUs_shumiao.pptx|Shumiao| |
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| 60 | |TR_3|lecture08_data_parallel_algorithm_demmel22_l pwang.pptx|lePing|graph_partition_shaobo.pptx|Shaobo| |
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| 61 | |TR_4|distributed_memory_machine_and_program_qiong.pptx|Qiong|Advanced_MPI_and_Collective_Communication_Algorithm_shumiao.pptx|Shumiao| |
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| 62 | |TR_5|densela_1_parallel_mat xi_multiplication_xyshi.pptx|Dr. Shi|-|-| |
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| 63 | |TR_6|Ray_A_universal_frame work_for_distributed_co mputing_stoica22_qingyu.pptx|QingYu|Sparse_Matrix_Vector_Multiply_SpMV_and_Iterative_Solvers_bowen.pptx|Bowen| |
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| 64 | |TR_7|Dynamic_Load_Balancing_demmel22_siyan.pptx|SiYan|parallel_graph_algorithm_Siqi_Chen.pptx|SiQi| |
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| 65 | 4 | jun chen | |
| 66 | ## EDA traveller 2023 |
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| 67 | 570 |
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| 68 | ### 2023 EDA Traveller Mar to May sessions |
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| 69 | 570 |
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| 70 | ### Group 1 VLSI and EDA flow: D Group winner top three: HaiAn(16), ZhengYu(12), Daisy(9)0 |
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| 73 | |--|--|--| |
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| 74 | |TR_01|TR_2023_01_CMOS_Logic.pptx|Qiong 2023/03/20| |
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| 75 | |TR_02|TR_2023_02_chip_fabrication.pptx|Daisy 2023/03/20| |
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| 76 | |TR_03|TR_2023_03floorplan_placement_Routing.pptx|JiaXiao, XiaoHu, SiYan 2023/03/21| |
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| 77 | |TR_04|TR_2023_04_Static_timing_analysis.pptx|ZhiHao, ZhenMing 2023/03/23| |
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| 78 | |TR_05|TR_2023_05_Chip_Finishing_Sign_Off.pptx|YingJie Tang, Sheng Huang 2023/03/27| |
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| 79 | |TR_06|TR_2023_06_sdp_Power_Analysis.pptx|ZhengYu Wang 2023/03/28| |
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| 80 | |TR_07|TR_2023_07_power_calculation_flow.pptx|LangYun Zeng 2023/03/28| |
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| 81 | |TR_08|TR_2023_08_IR_drop.pptx|ShuMiao Li 2023/04/10| |
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| 82 | |TR_09|TR_2023_09_low_power_UPF.pptx|XiJing Yao 2023/04/10| |
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| 83 | |TR_10|TR_2023_10_Free45nm_PDK_design.pptx|HaiAn 2023/04/11| |
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| 86 | **Note:** OCL PDK flow in: Verilog_to_manufacture_lecture , ZhenMing will follow up to setup HVP tutorial demo in cutbuild. |
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| 88 | ### Group 2 spice and liberty characterization D Group winner top three: LePing(15), LinJun(12), |
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| 89 | HaiAn(11)0 |
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| 92 | |--|--|--| |
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| 93 | |TR_11|TR_2023_11_spice_introduce_usage.pptx|JiaXiao 2023/04/13| |
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| 94 | |TR_12|TR_2023_12_SPICE_SIMULATION.pptx spice_simulation_case.zip|LePing2023/04/17| |
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| 95 | |TR_13|TR_2023_13_SPICE_NUMERIC_METHOD.pptx|JiaMin, Qiong 2023/04/18| |
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| 96 | |TR_14|TR_2023_14_klib_basic_knowledge.pptx|Danping 2023/04/20| |
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| 97 | |TR_15|TR_2023_15_intro_liberity.pptx TR_2023_15_k_lib_timing.pptx|LinJun 2023/04/24 and Hui 2023/04/24| |
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| 98 | |TR_16|TR_2023_16_Low_Power_Cell.pptx|ZhenMing 2023/04/25| |
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| 99 | |TR_17|TR_2023_17_Memory_IP_Macro.pptx|LangYun 2023/04/27| |
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| 100 | |TR_18|TR_2023_18_Free45nm_kl_ccsp.pptx|HaiAn 2023/04/27| |
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| 102 | (Homework: Why switching power is 0.5CVV?) why_sw_pow_is_0d5cvv.pptx |
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| 103 | TODO Ask SiQi to import demo k-lib flow into emir reg db and wiki #19681 |
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| 105 | ### Group 3 interconnection and signal integrity D Group winner top three: LePing(17), JiaMin(13), JingLin(12)0 |
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| 108 | |--|--|--| |
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| 109 | |TR_19|TR_2023_19_cmp_resistance_extract_flow.pptx|Jing Lin 2023/05/08| |
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| 110 | |TR_20|TR_2023_20_PG_wire_parasitic_and_extraction.pptx|ChunYan 2023/05/08| |
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| 111 | |TR_21|TR_2023_21_parasitic_and_spef.pptx.pptx|HaiAn 2023/05/29| |
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| 112 | |TR_22|TR_2023_22_signal_wire_delay_pi_rom.pptx|LePing 2023/05/30| |
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| 113 | |TR_23_a|TR_2023_23_CPM_introduction.pptx|WangYang Xiong 2023/06/01| |
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| 114 | |TR_23_b|TR_CPM_1_macro_model_based_on_MOR.pptx 00叩叩叩叩DD宏叩叩叩|JiaMin 2023/06/01| |
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| 115 | |TR_23_c|TR_CPM_2_MOR_model_order_reduction_20230511.pptx 0叩叩叩D叩|JiaMin 2023/06/01| |
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| 116 | |TR_24|TR_2023_24_CSM_introduction_20230605.pptx|WangYang Xiong 2023/06/05| |
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| 117 | |TR_25|TR_2023_25_IBIS_Intro.pptx|SiQi Chen 2023/06/08| |