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Locgic Synthesis » History » Version 3

jun chen, 03/04/2025 02:12 AM

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# Locgic Synthesis
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## Basic training
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attachment:"Lecture04 adder.pdf"
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attachment:"Lecture10_logical_effort.pdf"
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attachment:"Lecture20-adders.pdf"
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attachment:"Lecture21-multipliers.pdf"
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attachment:"Lecture23-count-shift.pdf"
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attachment:"ece667-LSyn-abc-comb.pdf"
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## Standards
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### HDL
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attachment:"IEEE 1364.1-2002 Verilog RTL Synthesis.pdf"
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attachment:"Verilog_IEEE.1364-2005.pdf"
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attachment:"VHDL-ieee-1076-2019.pdf"
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attachment:"System Verilog Spec 2017.pdf"
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### UPF
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attachment:"IEEE.1801-2009_UPF2.0.pdf"
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attachment:"IEEE.1801-2013_UPF2.1.pdf"
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attachment:"IEEE.1801-2015_UPF3.0.pdf"
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attachment:"IEEE.1801-2018.pdf"