Locgic Synthesis » History » Version 4
jun chen, 03/04/2025 02:17 AM
| 1 | 1 | jun chen | # Locgic Synthesis |
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| 2 | |||
| 3 | 3 | jun chen | -------------------------- |
| 4 | 4 | jun chen | |
| 5 | 3 | jun chen | ## Basic training |
| 6 | 1 | jun chen | |
| 7 | 4 | jun chen | **Mapped gate optimization** |
| 8 | |||
| 9 | 1 | jun chen | attachment:"Lecture10_logical_effort.pdf" |
| 10 | 4 | jun chen | attachment:"LE-talk-Harris.pdf" |
| 11 | |||
| 12 | **Boolean Optimization** |
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| 13 | |||
| 14 | attachment:"ece667-LSyn-abc-comb.pdf" |
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| 15 | attachment:"fpga10_speedup.pdf" |
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| 16 | attachment:"tech05_map.pdf" |
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| 17 | attachment:"dac05_mux.pdf" |
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| 18 | |||
| 19 | **Arithmetic Synthesis** |
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| 20 | |||
| 21 | 3 | jun chen | attachment:"Lecture20-adders.pdf" |
| 22 | 1 | jun chen | attachment:"Lecture21-multipliers.pdf" |
| 23 | attachment:"Lecture23-count-shift.pdf" |
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| 24 | 4 | jun chen | attachment:"Lecture04 adder.pdf" |
| 25 | attachment:"BK_adder.pdf" |
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| 26 | 1 | jun chen | |
| 27 | ------------------------ |
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| 28 | 2 | jun chen | |
| 29 | 1 | jun chen | ## Standards |
| 30 | |||
| 31 | 2 | jun chen | ### HDL |
| 32 | |||
| 33 | attachment:"IEEE 1364.1-2002 Verilog RTL Synthesis.pdf" |
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| 34 | attachment:"Verilog_IEEE.1364-2005.pdf" |
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| 35 | attachment:"VHDL-ieee-1076-2019.pdf" |
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| 36 | attachment:"System Verilog Spec 2017.pdf" |
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| 37 | |||
| 38 | |||
| 39 | ### UPF |
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| 40 | 1 | jun chen | |
| 41 | attachment:"IEEE.1801-2009_UPF2.0.pdf" |
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| 42 | attachment:"IEEE.1801-2013_UPF2.1.pdf" |
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| 43 | attachment:"IEEE.1801-2015_UPF3.0.pdf" |
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| 44 | attachment:"IEEE.1801-2018.pdf" |