Locgic Synthesis » History » Revision 4
Revision 3 (jun chen, 03/04/2025 02:12 AM) → Revision 4/5 (jun chen, 03/04/2025 02:17 AM)
# Locgic Synthesis -------------------------- ## Basic training **Mapped gate optimization** attachment:"Lecture04 adder.pdf" attachment:"Lecture10_logical_effort.pdf" attachment:"LE-talk-Harris.pdf" **Boolean Optimization** attachment:"ece667-LSyn-abc-comb.pdf" attachment:"fpga10_speedup.pdf" attachment:"tech05_map.pdf" attachment:"dac05_mux.pdf" **Arithmetic Synthesis** attachment:"Lecture20-adders.pdf" attachment:"Lecture21-multipliers.pdf" attachment:"Lecture23-count-shift.pdf" attachment:"Lecture04 adder.pdf" attachment:"BK_adder.pdf" attachment:"ece667-LSyn-abc-comb.pdf" ------------------------ ## Standards ### HDL attachment:"IEEE 1364.1-2002 Verilog RTL Synthesis.pdf" attachment:"Verilog_IEEE.1364-2005.pdf" attachment:"VHDL-ieee-1076-2019.pdf" attachment:"System Verilog Spec 2017.pdf" ### UPF attachment:"IEEE.1801-2009_UPF2.0.pdf" attachment:"IEEE.1801-2013_UPF2.1.pdf" attachment:"IEEE.1801-2015_UPF3.0.pdf" attachment:"IEEE.1801-2018.pdf"