Low power design flow and training¶

700

Low power implementation from Verilog to Layout¶

• Training lab location: /rnd1/jchen/newhire_training/lab/MVDD_labs/

• Check introduction slides low_power_upf.pptx

• Check training lab instructions MVDD_lab_instruction.pptx

• Another low power introduction from Bob 20220408 low_power_intro.docx

• Low Power Methodology Manual Low_Power_Methodology_For_System-on-Chip_Design.pdf

• Library Compiler User Guide (Library_Compiler_User_Guide_Modeling_Timing_Signal_lntegrity_and_Power_in_Technology_libraries_Version.pdf) in [[physical_design::EDA_Tool_Docs]]

Low power verification and UPF¶

TBD