Core_EDA

# Terminology 术语词条

## EDA Terminology {Initial from ZhenMing)

|  |  |  |

|--|--|--|

|VLSI	|Very Large Scale Integration	|D叩芯叩0DDDD |

|CTS	|Clock Tree Synthesis	|DODOO DDDDDDDDDDD |

|LVF	|Liberty Variation Format	|DDDDDDDDODD |

|MMMC	|Multi-Mode Multi-Corner	|芯叩工叩在叩DD叩(mode)DDD(corner)|

|OCV	|On Chip Variation	|ODDO造叩DDDODD |

|SOCV	|Statistical on Chip Variation	|DDDDDDDDDDDDDDDD |

|AOCV	|Advanced on Chip Variation	|DDDDDDDDDDDDDDDD |

|GBA	|Graph Based Analysis	|DDDDDDDOO;ODD叩DDDDDDDD |

|PBA	|Path Based Analysis	|DDDDDDDDDDDD |

|PVT	|Process Voltage Temperature	|ODDDD00D00 0DDDDDD |

|SDC	|Standard Design Constraint	|DDDDDDDDDDDDDDDODDD |

|SDF	|Standard Delay Format	|DDDDD叩到DD叩|

|SPEF	|Standard Parasitic Exchange Format	|DODDDDDDDDDDD |

|VCD	|Value Change Dump	|D叩DOD形DD |

|SAIF	|Switching Activity Interchange Format	|翻叩DDDDDDDDDD |

|TWF	|Timing Window File	|DDDDD果DD |

|SI	|Signal Integrity	|DODDDDDDDSID EMIR DDD SI|

|TNS	|Total Negative Slack	|DDDDDNS DDDDDDDDDDDDD |

|WNS	|Worst Negative Slack	|O叩D NSDDDDDOD |

|DRC	|Design Rule Check	|DDDD违叩检叩(叩叩DD;emDDD叩|

## SDC Terminology: SDC DOD 

## EMIR Terminology:

|  |  |

|--|--|

| Mintw	| Min VDD-VSS across all timing windows| 

| Efftw	| Min Average VDD-VSS across all timing window| 

| Maxtw	| Max VDD-VSS across all timing windows| 

| Minwc	| Min VDD-VSS across all clock cycles| 

| Maxwc	| Max VDD-VSS across all clock cycles| 

| Min_switching_win	| Min VDD-VSS across actual switching period| 

| Max_switching_win	| Max VDD-VSS across actual switching period| 

| EM	| Electronic Migration| 

| Pkg	| Package| 

| DMP	| Distributed Machine Process| 

| VP	| Vulcan Power| 

## Code Terminology

|  |  |

|--|--|

|ta;	|core timing engine|

|td;	|timing data|

|taTcl;	|timing commands|

|cdc;	|cell delay calculation|

|wdc;	|wire delay calculation|

|wdcTcl;	|wire delay commands|

|si;	|si analysis|

|ccs;	|ccs solver|

|rom;	|arnoldi rom (reduced order model)|

|sdc;	|sdc Sxxxxxxx design constraints|

|sdf;	|standard delay format|

|pba;	|path-based analysis|

|pow;	|power calculation|

|em;	|EM analysis code|

|ir;	|ir drop, resistance grid check code|

|xmath;	|solver, math code|

|powTcl;	|power tcl commands|

|emirTcl;	|IR drop resistance and qa commands|

|xmathTcl;	|solver commands|

## Code Terminology D rocsyn□

|  |  |

|--|--|

|vuTcl;	|For compile, elaborate commands|

|wuTcl;	|For synthesis optimization commands|

|xuTcl;	|For db commands|

|va;	|data structures, strings etc.|

|vif;	|Data structure for syntax units|

|vin;	|Verilog in and parse tree|

|vol;	|task, function, generate, parameters in verilog|

|we;	|sign full or parallel flag for case statement|

|win;	|Synthesis of special circuits□ mux, dff, lat|

|wl;	|lib cell handling|

|wr;	|syntax tree to general netlist|

|xd;	|convert database into AG database|

Files	

twwc.jpg	58.8 KB	2021-09-02	Jun CHEN

mttw.jpg	79 KB	2021-09-02	Jun CHEN