Core_EDA

Index by title

• Wiki
  • AI EDA
  • Basic timing analysis
    • 静态时序分析圣经翻译计划
  • DEA News to watch
  • Delay calculation and SI
  • EMIR
    • All about standards (SAIF SDC VCD DEF LEF etc)
    • Big Data Process
      • Cache view
      • CodeReview Guideline
      • Config
      • Developing with vesper
      • Get vesper
      • How does Vesper work
      • How to add Vesper worker
      • How to debug
      • How to design a c++ class used in both C++ and Python
      • How to modify ext directory
      • How to run cudf(GPU pandas) in VNC environment
      • How to validate qa failure
      • Hvp related
      • Known Issues
      • Logging related Macrofunction
      • Memory instances event filter rule
      • Python Training
      • QA
      • Recommend coding style
      • Reference data
      • Start with scons
      • Sub Module Introduction
      • Useful macros
      • Vesper crash issues
      • Vesper Scheduler GUI
      • Vesper Terminology
    • Cutting edge paper sharing
    • Database db dbProject
    • EDA Traveller
      • Solver Selected Topics
        • What is gather and scatter
        • 从麦克斯韦推导KCLKVL
        • 条件数
        • 消去树
        • 矩阵范数和误差
    • EM-IR and Power
      • DTH project trace
      • Electro Migration
        • EM analysis in VP
        • FIT
      • IR analysis
        • Chip Package Co-Simulation
        • Custom Model EMIR (Memory I0 PAD IP)
        • Dynamic IR analysis
        • High Performance IR Analysis
        • Reference Flow
        • Timing window file (twf)
      • Low power design flow and training
      • Power analysis
        • Debugging skill
        • High-level power estimation
        • Power save restore cache
        • Usage model
          • About glitch ans switching activity propagation
        • USDB support
      • RC parasitic extraction and LPE
      • Reporting and GUI for EMIR
        • Common GUI usage
        • GUI functions under plan
      • Thermal
      • Virtual power model (VPM)
    • EMIR New hire training
      • Setup shell alias and git config
      • Speed-up vim on huge file
      • Vim config
      • Vscode config
      • Xterm
    • Finite Element Analysis
    • History and moments
    • HPC and Matrix
      • Matrix collection
      • New Hire Training
      • Solver build and regression
      • Solver Tcl commands
        • Evaluate solver
        • Print matrix
        • Solver speedup test
    • Patent 专利
    • PV Center (Case Utility Infrastructure)
      • Failure verify SOP
      • Regression Testing Sop
    • Python training center
    • SPICE TEAM
      • Ngspice compiling method enhancement
      • Some tips for piece(Ngspice) user
    • Terminology 术语词条
    • Wall of Honer
  • Locgic Synthesis
  • Timing Analysis

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